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Altera_Forum
Honored Contributor
Honored ContributorMobile DDR
Hi together,
I´m a beginner in programming FPGAs. I want to use Mobile DDR SDRAM in my Design. This Mobile DDR (Micron) works normally with the I/O standard 1.8V LVCMOS. Unfortunately I am not able to compile my design with this I/O standard in combination with the DDR SDRAM high-performance controller. The suggestion of Quartus is to change the I/O standard to either HSTL or SSTL. Are these standards working with Mobile DDR which has the I/O standard 1.8V LVCMOS? Do I need to use the dedicated DQS and DQ pins or can I also use other I/O pins? It would be great to get helpful answers. Regards Spitzinger5 Replies
Altera_ForumWhat is the actual part you are using?
- Altera_Forum
I´m using a cyclone III ep3c16f484
- Altera_Forum
And what mobile ddr part number?
- Altera_Forum
Micron MT46H32M32LF
- Altera_ForumBest i can come up with, but basically answers your question. The altera core calculates all of it's timing values and operation based on a SSTL, so pretty sure won't work with your mobile device. Quartus is suggesting you change the io standard because that is what the core is designed to work with, not because it is what you should actually do. Haven't checked but there may also be differences in the actual operation of the two devices(mobile and non mobile) that would cause the core to not work. Sorry Kevin
