Forum Discussion
New Contributormipi csi2 tx, upper limit of video width
Hi, I am using Quartus ver 26.1 PRO Edition and investigating the MIPI CSI-2 TX IP on Agilex 5 E. I generated the CSI-2 Example Design and am running a RTL simulation. To change the video width, I modified the setting of FRAME_WIDTH_PIXELS in cfg_pkg.sv. When FRAME_WIDTH_PIXELS = 3840, the operation is normal. However, when FRAME_WIDTH_PIXELS = 7680, tready goes low and the system stalls. Is there an upper limit for FRAME_WIDTH_PIXELS?
The IP setting is follow:
15 Replies
yumadaHi Wincent,
Thank you for your reply.
I ran simulations for RAW8, RAW12, and RGB888 and obtained the following results. The testbenches for each case are included in the ZIP file I previously attached.
Similar to your results, RAW8 worked correctly even at 9600, but RAW12 failed at 9600.
Is there any way to make RAW12 also pass at 9600? Or is the maximum supported value fixed by the IP specification, with no available workaround?
Regards,
yumada
Wincent_AlteraRegular Contributor
Hi yumada -san,
Sorry for taking some time to get back to you.
We were able to reproduce the behavior and found that it is related to the line buffer depth in the CSI-2 Tx IP.
For the configurations you mentioned, the configured buffer is not large enough to hold a complete line of data with sufficient margin.
In this situation, the transmitter can stall before the first packet is produced. As a general guideline, the line buffer should be sized to at least two lines where possible, especially for wider image formats such as RAW12 and RGB888, which require more buffer space.
This limitation has been addressed in a newer release of Quartus v26.1.1 that supports larger buffer configurations.
Once the update done , the issue should be resolved.
Let me know if you have any other concern, thanks for pointing this out.
Regards,Wincent_Altera
- yumada
Hi Wincent,
Thank you very much for confirming that this issue will be resolved in v26.1.1.
I have one question. What will the maximum supported value be for the RAW12/RGB888 configuration?
I would like to confirm that it supports our specification. If you need our specific configuration details, I would like to request for private message support.
Regards,
yumada
- Wincent_Altera
Hi yumada -san,
Our MIPI design team is currently out of office.
I will keep follow up and get back to you shortly.
Please accept my apology for some delay.
Regards,
Wincent_Altera - Wincent_Altera
Hi yumada ,
I may need 3-4 days to investigate this, but will get back to you soon as possible once I have the any update.
Regards,
Wei Chuan
- yumada
Hi Wincent,
Are there any update on this?
Regards,
yumada- Wincent_Altera
Hi yumada ,
I've had problems getting the sim to run in that config, as the sim wasn't really designed to handle such long lines, it was only intended to demonstrate data flow I believe. As I can see a simple way to fix the main place it struggles. However, I don't see the issue that you reporting in that configuration - I can get 7680 pixel lines through CSI Tx in the stated configuration without seeing the input stall.
In RAW8 each pixel has 8 bits, which in the VVP streaming protocol is carried using 16-bits per pixel. So 4-PIP RAW8 requires a 64-bit wide data bus. But the cfg_pkg image and waveforms show a 96-bit data bus, which at 4 PIP implies 24-bits per pixel. Unfortunately, the image of cfg_pkg was cropped to hide the data type. For example, mine for the above was:
Regards,
Wincent- Wincent_Altera
- yumada
Hi Wincent,
I’m trying to attach my design but it seems to be getting ignored. Could you please let me know how I can send you the file?
- Wincent_Altera
Hi yumada ,
Can you please try to .zip the file and share it again ?
IF not , do appreciate if you can help to provide the IP configuration, and especially the data type that you are using,
Meanwhile, I am trying to replicate the issue --> get back to you soon as I have any finding.
Regards,
Wincent_Altera- yumada
Hi Wincent,
I was able to attach the ZIP file when I tried again today. Sorry for the trouble.
For the design, I changed the video format of mipi_csi2.ip, generated each example design, and ran simulations. The simulations were performed by modifying FRAME_WIDTH_PIXELS in cfg_pkg.sv.
I would appreciate it if you could take a look.Regards,
yumada
- Wincent_Altera
Hi yumada -san,
In RAW8 each pixel has 8 bits, which in the VVP streaming protocol is carried using 16-bits per pixel.
So 4-PIP RAW8 requires a 64-bit wide data bus. But the cfg_pkg image and waveforms show a 96-bit data bus, which at 4 PIP implies 24-bits per pixel. Unfortunately, the image of cfg_pkg was cropped to hide the data type. For example, ours for the above was:
Can I get your IP configuration(maybe a screenshot on the setting related to data type that you are using)./.qar will be better
so that we can replicate your setup and continue to investigate?
- yumada
Hi Wincent,
I apologize for the confusion. The data I previously attached was actually the result for RGB888. After changing the image format and frame width, I obtained the results shown in the table below. I have also attached the design that was used.
It appears that there may be some kind of upper limit.
I will attach my design.
- Wincent_Altera
Hi yumada-san,
Please allow me to have sometime to investigate this.
Get back to you shortly.
Regards,
Wincent_Altera
