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yumada's avatar
yumada
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2 months ago

mipi csi2 tx, upper limit of video width

Hi, I am using Quartus ver 26.1 PRO Edition and investigating the MIPI CSI-2 TX IP on Agilex 5 E.  I generated the CSI-2 Example Design and am running a RTL simulation. To change the video width, I m...
mipi
Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
1 month ago

Hi yumada -san,

Sorry for taking some time to get back to you.
We were able to reproduce the behavior and found that it is related to the line buffer depth in the CSI-2 Tx IP. 
For the configurations you mentioned, the configured buffer is not large enough to hold a complete line of data with sufficient margin. 
In this situation, the transmitter can stall before the first packet is produced. As a general guideline, the line buffer should be sized to at least two lines where possible, especially for wider image formats such as RAW12 and RGB888, which require more buffer space. 

This limitation has been addressed in a newer release of Quartus v26.1.1 that supports larger buffer configurations.
Once the update done , the issue should be resolved. 
Let me know if you have any other concern, thanks for pointing this out.

Regards,

Wincent_Altera

yumada's avatar
yumada
Icon for New Contributor rankNew Contributor
1 month ago

Hi Wincent,

Thank you very much for confirming that this issue will be resolved in v26.1.1.
I have one question. What will the maximum supported value be for the RAW12/RGB888 configuration?
I would like to confirm that it supports our specification. If you need our specific configuration details, I would like to request for private message support.

Regards,
yumada

  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    1 month ago

    Hi yumada -san,

    Please check your private inbox .

    Regards,
    Wincent_Altera