Altera_Forum
Honored Contributor
Honored Contributormem_clk and mem_clk_n
Why the mem_clk signals are declared as bidirectional(inout) in rtl code of DDR/DDR2 memory IP?
Forum Discussion
1 Reply
Altera_ForumIts for a self calibrating mimic path. Check out this link
http://www.altera.com/support/kdb/solutions/rd08162007_376.html
