MAX10 Development kit LVDS TX assignments

I'm currently using the MAX10 development kit, and I'm trying to interface with two external components.

In order to have a stable clock circuit, I use the "external" clock source on the MAX10 Development kit, and run it trough a PLL on the FPGA to derive different clocks.

Now, I want to output some of these clock signals using the HSMC_CLK_OUT_n/p[1,2] signals.

Ideally I want the clock frequency to be at 50MHz, but I've been unable to create stable signals on the output pins of unless I tune the clock down to 8MHz. I've checked the assignments, and the pins themselves are assigned to LVDS, so from what I can gather the FPGA should be able to handle 50MHz switching?

My current signal path is this External_CLK => SRCCLKPLL => ALTERA_GPIO_LITE => Output_pin.

Do i need any additional blocks internally on the FPGA? Am I going about this the right way, or is there a simpler way to get a stable, synced clock output off the MAX10 devkit?