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KRoma6's avatar
KRoma6
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5 years ago

LVDS SERDES using external PLL from IOPLL

Hello, I am using the LVDS SERDES IP with external PLL provided by the IOPLL. I configured the IOPLL as recommended in the LVDS SERDES IP for Cyclone 10 GX but I am getting an error: "ext_<clock ...
KRoma6's avatar
KRoma6
Icon for New Contributor rankNew Contributor
5 years ago

Hi JonWay,

Yes I tried both options for the "Access to PLL LVDS_CLK/LOADEN output port": <"LOADEN 0" and "LOADEN 0 & 1">.

So you want to export these signals and connect them within a module?

JonWay_altera's avatar
JonWay_altera
Icon for Frequent Contributor rankFrequent Contributor
5 years ago

Generate HDL for both the LVDS and PLL IP. Create a top RTL file and instantiate both IPs there. Connect them together by RTL coding. Check if the problem is still there or not.