LDPC coder issues...

During compilation, I find many of these warnings ...are all related to internal IP questions....

Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "layer_E_sum" into its bus

It is due to my device selection or other???

UPDATE II, I hope te be helpful for someone...

I corrected QSYS enc,dec declaring on QUartus project and now Modelsim find the enc/dec models.. but Modelsim FAILS when read the encoder .sv file, finding a:

Syntax error, unexpected non-printable character with the hex value '0x8b' (!)

But this file .sv is unreadable... it is created from QSYS !! What's a bunch of confusion ... :-(

UPDATE III

- Altera support doesn't run... :-( I attempt to fill all requested infos (job, mail etc but web page not upload the change and runs always with old data.

- I send a service request but it is impossible to enter in my support, web page make an error "too many redirects"... I try to clean all cookies, I use 2 pc and a android phone : the result is the same "the page doesn't run" (!!!!!!!!!!!!)

- I try these LDPC IP on a cyclonV dev kit.. well, without any support and any doc about coder and encoder..

* How I can set LLR and SOFT for decoder ??? It seem's decided from encoder , in some hidden manner. I found a _pkg.vhd file inside encoder directoris, and inside it there are LLR/SOFT decided when qsys create the ip (LLR=2,SOFT=3)

* Well, I set decoder for LLR=2, SOFT=3, but data width input is fixed now to 6 and output is costrained to 2 (!!!)

* I try to runs Enc + Dec on testbench running on Cyclone V E dev kit. I see with signal tap that Clocks, start/end of packet of 960/6 = 160 words are correct but the encoder doesn't live !!!!!!! Ready signals are 0, as per data out....

IN MY HUMBLE OPINION, THIS IS NOT PROFESSIONAL ....WHY I MUST WORK WITHOUT ANY DETAILED TECH SPEC DOCS ABOUT THESE IP?????

I must imagine parameters settings, behaviour and so on...

(I WORKED WITH XILINX IP , DOC & SUPPORT WAS OF OTHER PLANET :-((((((((((

UPDATE IV after unlocking my account I have finally a response from ALTERA (Thanks to mr Chen) .. there is a bug on quartus... enc - dec libraries are call from modelsim twice (!) . I solved posing# comment on the twice lines over .do file and re-launch it from modelsim.. now it runs. Now there is the problem to understand coder - encoder behaviour without documentation.. (!!))

On my simulation, I generate a packet of 960 bit, word = 6 bit. Coder receive the eop/sop and the packet. Then it give in_ready=0 (ok..), after 7 clock cycles raises "out_valid" (ok).. but out data is all zeros (!!!!!).

I try to change input data on rising or falling edge... nothing!

Eop and Sop are pulses 1 cycle time, eop is on first packet word, sop is on last packet word.. But encoder doesn't run (!!!!)

:mad::mad:

I redesign data test generator. Giving a 160 words, 6 bit each, Sop/EoP pulses rising edge on first and last data, CODER NOW RUNS.

It generates 1320 bit in symbols 6 bit, with related SoP/EoP

I give these data to decoder with all parameters (LLR,SOFT, PAR etc) set as per coder.

Well, decoder runs, it gives a 2 bit streaming, total of 960 bit with SoP/Eop and out_valid asserted. Well, data are not coherent with input coder data.... I'm waiting for support... :-0

Why documentation about these IP are so poor????