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Altera_Forum
Honored Contributor
Honored ContributorLDPC coder issues...
Hi, people! I'm attempt to simulate LDPC coder-encoder IP, set as wimedia 960-1320 I make a testbench with data generator for simple counter 10 bit. I generate 96 word (960 bit) packet with sta...
Altera_ForumHonored Contributor
Honored ContributorUPDATE IV after unlocking my account I have finally a response from ALTERA (Thanks to mr Chen) .. there is a bug on quartus... enc - dec libraries are call from modelsim twice (!) . I solved posing# comment on the twice lines over .do file and re-launch it from modelsim.. now it runs. Now there is the problem to understand coder - encoder behaviour without documentation.. (!!))
On my simulation, I generate a packet of 960 bit, word = 6 bit. Coder receive the eop/sop and the packet. Then it give in_ready=0 (ok..), after 7 clock cycles raises "out_valid" (ok).. but out data is all zeros (!!!!!). I try to change input data on rising or falling edge... nothing! Eop and Sop are pulses 1 cycle time, eop is on first packet word, sop is on last packet word.. But encoder doesn't run (!!!!) :mad::mad:
