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Altera_Forum
Honored Contributor
Honored ContributorLDPC coder issues...
Hi, people! I'm attempt to simulate LDPC coder-encoder IP, set as wimedia 960-1320 I make a testbench with data generator for simple counter 10 bit. I generate 96 word (960 bit) packet with sta...
Altera_ForumHonored Contributor
Honored ContributorDuring compilation, I find many of these warnings ...are all related to internal IP questions....
Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "layer_E_sum" into its bus It is due to my device selection or other???
