Honored ContributorHi,
Does Altera have an appnote or a design example for implementing a JTAG master in its FPGA? The objective is to create an IP that allows Nios II to program external devices through 8 bit parallel interface, the IP will generate the JTAG bitstream signals to interface with external devices directly. Thanks, Hua
Honored ContributorIt depends on what device you want to program.
If the device is something you have the JTAG instructions for, then a JTAG master is just programmable I/O. If you want to program Altera FPGAs, then there is a problem; the JTAG programming sequence, in terms of toggles of TMS/TCK/TDI, is proprietary information, so it not directly available, but there is a solution. The solution Altera provides is called Jam/STAPL. Altera provides reference source code that you can modify to replace the JTAG toggle routines with your own toggle routines. I have ported this code several times to program MAX II devices and EPC2 devices via the PCI bus (with TCK/TMS/TDI/TDO signals exposed via digital I/O registers on each board), but the host has always been an x86 processor (running Linux). I'm not sure how well the code will port to say the NIOS II processor. File an Altera SR and ask. Search on Altera's site for 'Jam Player' and you'll find jp_25.exe You could always try building the code with gcc for NIOS II and see if it compiles. Cheers, DaveHonored ContributorIf you are using an FPGA to program another FPGA, and you have access to the configuration pins on the FPGA you are trying to program, then its pretty easy to write a programmer, eg. Altera has the Parallel Flash Loader (PFL) IP core, and I have written my own version of a similar core:
http://www.ovro.caltech.edu/~dwh/carma_board/fpga_configuration.pdf (http://www.ovro.caltech.edu/%7edwh/carma_board/fpga_configuration.pdf) Cheers, Dave
