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Honored Contributor
Honored ContributorJTAG Master
Hi, Does Altera have an appnote or a design example for implementing a JTAG master in its FPGA? The objective is to create an IP that allows Nios II to program external devices through 8 bit pa...
Altera_ForumHonored Contributor
Honored ContributorIf you are using an FPGA to program another FPGA, and you have access to the configuration pins on the FPGA you are trying to program, then its pretty easy to write a programmer, eg. Altera has the Parallel Flash Loader (PFL) IP core, and I have written my own version of a similar core:
http://www.ovro.caltech.edu/~dwh/carma_board/fpga_configuration.pdf (http://www.ovro.caltech.edu/%7edwh/carma_board/fpga_configuration.pdf) Cheers, Dave
