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Rleduc's avatar
Rleduc
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2 years ago
Solved

JESD204B IP (RX) - K28 character not recognized

Hello dear community,

With Arria 10 SoC-FPGA (Terasic HAN Pilot Plateform), I try to receive data from ADC (AD9250) that sends serialized data on 2 lanes with JESD204B protocol.

I properly set up the ADC configuration, and made sure that jesd parameters between ADC and JESD204B IP core are the same, which are the followings :

- Sampling frequency = 125 MSPS

- SYSREF = 7,8125 MHz

- L=2, M=2, N=14, N'=16, F=2, K=16, Scramble disabled.

I can visualize the K28 characters, (0xBC) on oscilloscope after 8b/10b encoding.

However, the transmission never goes out of CGS phase (SYNC is kept to 0). Actually, I can read the frames on the Signal Tap Logic Analyzer , as in the following screenshot. The register I could read in order to visualize the K28 characters is the "rx_parallel_data[79..0]", since I'm not allowed to directly read on serial lanes input.

Not sure if we can read properly, but the parallel data is "06BE5" four times which is indeed 80 bits. This shows, to my sense, 2 "samples" (2 times K28+/-) for 2 lanes, which are synchronised since we have the same value which is read.

I did the conversion and 06BE5 is exactly the K28 character after 8b10b, but shifted from 3 bits.

So this is, I believe due to a fail for the JESD204B RX (FPGA) to understand where is the beginning of the K28 character. And actually, that is a question where I couldn't find the answer in the jesd204b user guide.

Also, I don't see any error in the jesd204b_rx registers (0x60 and 0x64) so I don't know where I should look for in order to solve this synchronisation issue on the receiving side ?

Thank you,

  • skbeh's avatar
    skbeh
    2 years ago

    Hi Roman


    It looks like you are facing SYNCN signal not de-aserted issue, hence the K28 character not being recognized.

    You can refer to below Fault Tree Analysis (FTA) of JESD204B SYNCN Signal to determine the possible root causes.


    Fault Tree Analysis (FTA) JESD204B SYNCN Signal Not De-asserted link:

    https://community.intel.com/t5/FPGA-Wiki/FTA-JESD204B-SYNCN-Signal-Not-De-asserted-Issue/ta-p/735963


    This FTA_JESD204B_sync_n_not_de-assert consists of a FTA diagram and table used to debug and root cause the SYNC_N signal not de-asserted issue happens in the JESD204B subsystem. In the FTA diagram, multiple hypothesis are made based on the failure symptom as described. For each of the hypothesis, it can have 2nd level or up to 3rd level suspects.


    Hope this helps.


    Regards

    Soon


4 Replies

  • skbeh's avatar
    skbeh
    Icon for Contributor rankContributor
    2 years ago

    Hi Roman


    It looks like you are facing SYNCN signal not de-aserted issue, hence the K28 character not being recognized.

    You can refer to below Fault Tree Analysis (FTA) of JESD204B SYNCN Signal to determine the possible root causes.


    Fault Tree Analysis (FTA) JESD204B SYNCN Signal Not De-asserted link:

    https://community.intel.com/t5/FPGA-Wiki/FTA-JESD204B-SYNCN-Signal-Not-De-asserted-Issue/ta-p/735963


    This FTA_JESD204B_sync_n_not_de-assert consists of a FTA diagram and table used to debug and root cause the SYNC_N signal not de-asserted issue happens in the JESD204B subsystem. In the FTA diagram, multiple hypothesis are made based on the failure symptom as described. For each of the hypothesis, it can have 2nd level or up to 3rd level suspects.


    Hope this helps.


    Regards

    Soon


  • Rleduc's avatar
    Rleduc
    Icon for New Contributor rankNew Contributor
    2 years ago

    Hi Soon,

    Thank you for your answer, I didn't know about this FTA. Thanks to this, I double checked if my SYSREF signal which I suppose has an issue in assignment.

    What was mistaking, is that in SignalTap I can see the SYSREF signal, which is LVDS input, and I was only looking at the positive signal of the differential pair. Turns out that the negative one wasn't assigned surprisingly ! So the FPGA was only seeing half of the expected amplitude

    It works perfectly like magic now, it directly switched to data transmission phase with good ILAS parameters.

    I was just curious about some status registers of jesd204b core, that can be found in jesd204b core datasheet p.147, rx_status4 and rx_status5. They mention that this is the current state of RX DLL code group synchronization and frame synchronization state machine, but I couldn't find somewhere the explanation of the value ? For instance I get 0xA for both these regs.

    Anyway thanks for big help !

  • skbeh's avatar
    skbeh
    Icon for Contributor rankContributor
    2 years ago

    Hi Roman

    Regarding the questions about rx_status4 and rx_status5 registers:
    rx_status4 is the current state of the "Code Group Synchronization" state machine from the JESD204B spec shown here:

    The encoding is as follows:
    CS_INIT = 2'b00
    CS_CHECK = 2'b01
    CS_DATA = 2'b10

    Similarly, rx_status5 reflects the current state of the "Frame Synchronization" state machine shown here:

    Note that in practice, these (2) registers might not necessary to be used for any meaningful debug. The suggestion is to use the rx_err0 and rx_err1 registers and perhaps a signaltap of the PCS data and status bits as shown in Figure 33 of the JESD204B user guide.

  • Rleduc's avatar
    Rleduc
    Icon for New Contributor rankNew Contributor
    2 years ago

    Hey,

    Thanks for the usueful response, at least I know what it stands for !

    I close this topic,

    Best regards