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Rleduc's avatar
Rleduc
Icon for New Contributor rankNew Contributor
3 years ago
Solved

JESD204B IP (RX) - K28 character not recognized

Hello dear community, With Arria 10 SoC-FPGA (Terasic HAN Pilot Plateform), I try to receive data from ADC (AD9250) that sends serialized data on 2 lanes with JESD204B protocol. I properly set ...
  • skbeh's avatar
    skbeh
    3 years ago

    Hi Roman


    It looks like you are facing SYNCN signal not de-aserted issue, hence the K28 character not being recognized.

    You can refer to below Fault Tree Analysis (FTA) of JESD204B SYNCN Signal to determine the possible root causes.


    Fault Tree Analysis (FTA) JESD204B SYNCN Signal Not De-asserted link:

    https://community.intel.com/t5/FPGA-Wiki/FTA-JESD204B-SYNCN-Signal-Not-De-asserted-Issue/ta-p/735963


    This FTA_JESD204B_sync_n_not_de-assert consists of a FTA diagram and table used to debug and root cause the SYNC_N signal not de-asserted issue happens in the JESD204B subsystem. In the FTA diagram, multiple hypothesis are made based on the failure symptom as described. For each of the hypothesis, it can have 2nd level or up to 3rd level suspects.


    Hope this helps.


    Regards

    Soon


Rleduc's avatar
Rleduc
Icon for New Contributor rankNew Contributor
3 years ago

Hi Soon,

Thank you for your answer, I didn't know about this FTA. Thanks to this, I double checked if my SYSREF signal which I suppose has an issue in assignment.

What was mistaking, is that in SignalTap I can see the SYSREF signal, which is LVDS input, and I was only looking at the positive signal of the differential pair. Turns out that the negative one wasn't assigned surprisingly ! So the FPGA was only seeing half of the expected amplitude

It works perfectly like magic now, it directly switched to data transmission phase with good ILAS parameters.

I was just curious about some status registers of jesd204b core, that can be found in jesd204b core datasheet p.147, rx_status4 and rx_status5. They mention that this is the current state of RX DLL code group synchronization and frame synchronization state machine, but I couldn't find somewhere the explanation of the value ? For instance I get 0xA for both these regs.

Anyway thanks for big help !