jesd204b IP core have problem

Question

When I use the altera_jesd204 IP core in my procedure ,I  try to use modelsim-altera to do RTL simulations .Then I find this problem.When the modelsim compiles the altera_jesd204_8b10b_dec.v ,it find two syntax errors.But the license don't include viewing support, so I have no idea what should I do to continue my RTL simulation?

altera_forum · Answer

Hi,

Looking at the error messages, it seems like there is some internal issue with the IP .v files. Just wonder which version you are using? You might want to try the latest version to see if it works.

altera_forum · Answer

My Quartus ii version is 13.1,and the IP is for this version too.So may be I should try Quartus II 14.0?

altera_forum · Answer

Hi,  The latest Quartus II version is 15.0. It would be great if you could try with the latest version.

Forum Discussion

jesd204b IP core have problem

3 Replies

Recent Discussions

Correct way to configure the RGMII input and output pins on a MAX10 FPGA

PCIe Enumeration Failure for CXL IP

Behavior of 10 GX Avalon-MM Interface for PCI Express* IP Core when byteenable=16'h0000

Regarding MIPI CSI 2 TX

How to Prevent Agilex 7 F-tile PMA Direct PHY TX Lane Skew