New ContributorIssue with Simulation Stalling in Intel P-Tile Streaming PCIe Gen4 x8 Example Design
Hi everyone,
I generated the Intel P-tile Streaming IP example design using different Quartus versions (23.3, 24.1, and 23.2), selecting a Stratix board that supports P-tile. In the IP catalog, I chose the P-Tile Streaming PCIe IP. For configuration, I set the PCIe to Gen 4 1x8 256 interface, leaving the other options at their default settings. After generating the example design, I simulated it in QuestaSim version 24.1, following the steps: do msim_setup.tcl -> ld_debug -> run -all. The simulation started, but at some point, it got stuck.
After approximately 1.5 hours in simulation time, I noticed the following info message: "RP USER AVMM DRIVER: begin RP Configuration."
For debugging, I added some prints and found that the simulation is stuck waiting for the wait_request signal to deassert from the Root Port BFM. I'm not sure how to proceed with debugging from here.
Any advice on how to resolve this issue?
Hi,
I am Wincent, Application Engineer from Altera.
We sincerely apologize for the inconvenience caused by the delay in addressing your Forum queries.
Due to an unexpected back-end issue in our system, your Forum case, did not reach us as intended.
May I know which Questasim version that you are using?
There is an known issue we try to fix for the P-tile simulation tools.
To work around this problem, use Siemens* Questa Sim-64 2022.2. Starting in the Intel® Quartus® Prime Software version 23.3, solve this issue by adding this command " set USER_DEFINED_ELAB_OPTIONS "-voptargs=\"-noprotectopt\" before running simulation in the Siemens* Questa Sim.
Detail you may refer to https://www.intel.com/content/www/us/en/support/programmable/articles/000092901.html
Hope that is able to help you to move forward,
Regards,
Wincent_Intel
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