Forum Discussion
New ContributorIssue with Simulation Stalling in Intel P-Tile Streaming PCIe Gen4 x8 Example Design
Hi,
I am Wincent, Application Engineer from Altera.
We sincerely apologize for the inconvenience caused by the delay in addressing your Forum queries.
Due to an unexpected back-end issue in our system, your Forum case, did not reach us as intended.
May I know which Questasim version that you are using?
There is an known issue we try to fix for the P-tile simulation tools.
To work around this problem, use Siemens* Questa Sim-64 2022.2. Starting in the Intel® Quartus® Prime Software version 23.3, solve this issue by adding this command " set USER_DEFINED_ELAB_OPTIONS "-voptargs=\"-noprotectopt\" before running simulation in the Siemens* Questa Sim.
Detail you may refer to https://www.intel.com/content/www/us/en/support/programmable/articles/000092901.html
Hope that is able to help you to move forward,
Regards,
Wincent_Intel
New ContributorHi Wincent,
Thank you for your prompt response and for providing the workaround. I appreciate your help.
I am currently using Questasim version 22.4. I applied the suggested solution with the command set USER_DEFINED_ELAB_OPTIONS "-voptargs=-noprotectopt" in Questsim 22.1, and the simulation completed successfully.
Thanks also for sharing the reference link
Regular ContributorHi Thanavignesh,
Glad that my suggestion is able to help to resolved the problem you facing.
Therefore, I will close this cases, the rest will transitioned to community support.
If you have any new question, feel free to file an new forum support, we will try our best to assist
If your support experience falls below a 9 out of 10, I kindly request the opportunity to rectify it before concluding our interaction. If the issue cannot be resolved, please inform me via this forum page of the cause so that I can learn from it and strive to enhance the quality of future service experiences.
Wincent_Intel
p/s: If any answer from the community or Intel Support is helpful, please feel free to give the best answer or rate 9/10 survey.
- thanavignesh
Hi Wincent,
I simulated the example design generated in Quartus 23.3 using Questa Intel FPGA version 23.2. It took approximately 4.5 hours to reach the first log info:
INFO: 126725 ns RP User Avmm Driver: begin RP Configuration.
The simulation completed successfully after about 9 hours, with the final log :
INFO: 242847 ns PIO ED MWr/Mrd Completed.
SUCCESS: Simulation stopped due to successful completion.- Is there any way to reduce the overall simulation time?
- What processes are running in the background before the 126725 ns mark?
- Is there any documentation available that explains the activities happening during this period?
- Wincent_Altera
Hi,
- Is there any way to reduce the overall simulation time?
- For F-tile we do have a FastSIM mode https://www.intel.com/content/www/us/en/docs/programmable/683140/22-4-8-0-0/fastsim-mode-support.html . but the features is not available to P-tile
- Did you add all signal to the simulation model ?
- If you need a faster simulation completion time, perhaps you can add few only signal that you need to monitor for example pin_perst, ltssm, gen speed/width and other pcie related signal.
- What processes are running in the background before the 126725 ns mark?
- I think the background process is written in the scripts of simulation. Other than that we do not have specific indicator to shows that.
- Is there any documentation available that explains the activities happening during this period?
- Is there any specific reason you need to know what happen ?
Regards,
Wincent- thanavignesh
Hi wincent,
1.Is there any specific reason you need to know what happen ?Yes Understanding from Link Training and Process Flow
Can you explain how the process starts for link training in the code and how and where the subsequent tasks are called in the BFM for both the Root Port (RP) and Endpoint (EP)? I’d like to understand how the process begins and progresses
2.When using the option set USER_DEFINED_ELAB_OPTIONS "-voptargs=\"-noprotectopt\" in msim_setup.tcl:- If I run ld_debug and run -all, it takes 4.5 hours to reach the log message: INFO: 126725 ns RP User Avmm Driver: begin RP Configuration, and the simulation finishes after 4.5 hours.
- If I use ld and run -all, it takes 40 minutes to reach the same message INFO: 126725 ns RP User Avmm Driver: begin RP Configuration, but the simulation seems to get stuck afterward with no further logs waiting for the wait_request signal to deassert from the Root Port BFM..
What could be causing these differences, and how can I ensure smooth simulation without getting stuck?
3.Warning About Optimizations
When running msim_setup.tcl and ld_debug I get this warning:
Warning: (vopt-10587) Some optimizations are turned off because the +acc switch is in effect. This will cause your simulation to run slowly. Please use -access/-debug to maintain needed visibility.
How can I avoid this warning while maintaining necessary visibility without impacting simulation performance? Could this warning be related to the delays I’m experiencing?
4. Reset_status_n Signal Delay
In the simulation waveform ,One observation is the p0_reset_status_n signal remains low for approximately 100,000 ns, which seems to delay progress. Are there any adjustments or optimizations to reduce this reset assertion time? Could this be the case delay I’m experiencing?
- Is there any way to reduce the overall simulation time?
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