Issue with BSP Creation for Nios-V/m Using LPDDR4 on Agilex-5 (Quartus 24.1 & 24.3.1)

Hello,

We received the hardware earlier than expected, so we are continuing the discussion in this thread/ticket.

Unfortunately, we were unable to use the EMIF IP (LPDDR4) as the program memory for the Nios-V processor to run/debug our application using the Ashling RiscFree IDE on an Agilex-5 FPGA.

Here is a summary of the tests we performed:

• Using on-chip RAM as program memory: We successfully ran and debugged our application with the Nios-V processor using Ashling RiscFree IDE.
• With on-chip RAM as program memory, we connected the processor’s data bus to the Address Span Extender linked to the EMIF. We were able to allocate and access LPDDR4 memory without issues. Write/read tests on multiple memory locations of the LPDDR4 were successful.
• When both the data and instruction buses of the Nios-V processor were connected to the Address Span Extender (linked to the EMIF), and we set the Address Span Extender as the Reset Agent in the Nios-V Processor configuration (in parameters' editor), we attempted to use LPDDR4 as program memory. However, running/debugging from Ashling RiscFree IDE failed. A screenshot of the error is attached.

It is worth mentioning that on Agilex 7, we successfully used DDR4 memory—connected via an EMIF IP core and linked through the Address Span Extender—as the program memory for the Nios-V processor, and were able to run and debug applications using the Ashling RiscFree IDE.

Could you please advise how to resolve this issue on Agilex-5?

Also, could you confirm whether this procedure has been successfully validated on your side using real hardware?

Best regards,