Issue with BSP Creation for Nios-V/m Using LPDDR4 on Agilex-5 (Quartus 24.1 & 24.3.1)

Hello,

You're not seeing the "_windowed_slave" suffix because the "cntl" port of the Address Span Extender is not connected to the "data_manager" port of the processor. This connection is typically required to allow the processor to modify the Address Span Extender's settings if needed.

Also, you're not seeing a warning in the "Problems" tab because the altera_address_span_extender_hw.tcl file located at:
<install_dir>/ip/altera/merlin/altera_address_span_extender
was not modified as described in the following Intel forum post:
https://community.intel.com/t5/Programmable-Devices/NIOSII-using-the-FPGA-to-HPS-SDRAM-Bridge-via-Address-Span/td-p/150256

As previously mentioned, we need to remove the # character from the following lines to enable automatic detection of the memory device:

#set_interface_assignment windowed_slave embeddedsw.configuration.isMemoryDevice 1  
#set_interface_assignment windowed_slave embeddedsw.configuration.affectsTransactionsOnMasters "expanded_master"  

We have now reinserted the # character before the second line, and as a result, the warning no longer appears.

Please note that removing the # from both lines used to work fine with Agilex 7 FPGAs.

Thanks again for your help!
You can go ahead and close this ticket.
We’ll test the generated BSP for Agilex 5 soon, and if we encounter any issues, we’ll open a new ticket.

Best regards,