Issue with BSP Creation for Nios-V/m Using LPDDR4 on Agilex-5 (Quartus 24.1 & 24.3.1)

Hello,

The issue regarding BSP creation when the TSE IP cores are instantiated in QSYS subsystems was observed in Quartus 24.1. Additionally, we encountered other BSP-related issues when the TSE IP core was instantiated in the design. For example, the information provided in the system.h file of the generated BSP, corresponding to the TSE IP core, does not appear to be correct.

These issues do NOT occur when using Quartus 24.3.1. Therefore, they are already resolved by Intel in the latest released Quartus.

However, in both Quartus versions, when the BSP is valid, we consistently receive the following warning after BSP generation:

⚠ WARNING:
"Master 'expanded_master' of module 'address_span_extender' published by embeddedsw.configuration.affectsTransactionsOnMasters embedded software assignment on slave 'windowed_slave' doesn't exist."

Does this warning require special attention?

Following the instructions from the Intel community thread link provided in our earlier message, we removed the # character from the following lines in the "altera_address_span_extender_hw.tcl" file located at:
<install_dir>/ip/altera/merlin/altera_address_span_extender

set_interface_assignment windowed_slave embeddedsw.configuration.isMemoryDevice 1  
set_interface_assignment windowed_slave embeddedsw.configuration.affectsTransactionsOnMasters "expanded_master"  

Without updating "altera_address_span_extender_hw.tcl", we could not see the "address span extender" as the visible memory of the processor for generating the BSP.

Additionally, please note that we are using DDR memory as the main memory for the Nios-V processor, with the address span extender placed between the processor and the DDR controller. We already have a similar system working on an Agilex-7 FPGA, and we are now upgrading the design for Agilex-5.

We don't receive the same warning when we generate the BSP for the Agilex-7 FPGA using Quartus 23.4.

Best regards.