Issue with 245 Fifo sync mode

Do you monitor RXF on falling edge of clock?

See

http://electro-logic.blogspot.it/2014/03/fpga-comunicazione-ad-alta-velocita_1.html

And let us know

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Dear All,

I am actually working on a communication chain between a FPGA and a FT2232H chip. So, the goal is to send a file from PC to FPGA, store it in a FIFO memory and then receive the sent data to PC.

I am using the 245 fifo sync mode.

All is working fine, expect that I rarely have a lose of one byte that appears randomly.

So for example, when I send a packet of 512byte, i received well the 512byte but when I repeat this operations 200 times, I noticed that sometimes I only receive 511 byte and when I check where happens the lost byte, it happens randomly. And when I send a packet of 65.536 byte, again sometimes, I only received 65 535 byte.

The strange thing is that when a lose occurs, this is always one byte.

Can anyone help out me there to solve this problem ?

Attached you will find my VHDL code.

Thank you for your help !

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