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Altera_Forum's avatar
Altera_Forum
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18 years ago

Is there a Pipelined bridge for Quartus 6.0?

Does anyone know if the Pipeline Bridge component for the current versions of Quartus II is available as a version 6.0 SOPC component? I'm trying to speed up fmax on nios2 to 100Mhz on a Cyclone II grade -8, by separating it from the sdram (SDR) and other periferals. I want to operate the rest of the design at the maximum available 133Mhz... any ideas? So far I can only get to about 95 Mhz on Nios2.

--Daniel

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    18 years ago

    Yes, I have already tried these bridges with little to poorer performance. I noticed that there was an exported Read_Write_Full signal to the SOPC top level. That seemed wrong. Almost like that signal should have been tied to Avalon for wait state generation.

    Anyhow, I have a VGA dma master which cannot function below 110Mhz, and I'm quite sure that I'll never achieve that with the nios2 in my current device; even if I place all other periferals behind the bridge. I tried operating nios2 in a slower clock domain, but we all know what kind of penalty this causes in terms of clock cycles per transfer....completly unacceptable. On a side note, I recall reading or hearing somewhere that the generated ram cannot operate at these frequencies. Can anyone confirm, so I don't have to hunt the datasheet down?