Is there a Pipelined bridge for Quartus 6.0?

Yes, I have already tried these bridges with little to poorer performance. I noticed that there was an exported Read_Write_Full signal to the SOPC top level. That seemed wrong. Almost like that signal should have been tied to Avalon for wait state generation.

Anyhow, I have a VGA dma master which cannot function below 110Mhz, and I'm quite sure that I'll never achieve that with the nios2 in my current device; even if I place all other periferals behind the bridge. I tried operating nios2 in a slower clock domain, but we all know what kind of penalty this causes in terms of clock cycles per transfer....completly unacceptable. On a side note, I recall reading or hearing somewhere that the generated ram cannot operate at these frequencies. Can anyone confirm, so I don't have to hunt the datasheet down?