Forum Discussion
New ContributorIs it allowed to connect two pll inclk0 to the same input clock ?
Hi,
I have a design on a EP4CE40 FPGA where I instantiated a second pll and mapped the inclk0 input to the same input clock as the first one. I get a Critical Warning (176598): PLL "pll3:inst_pll2|altpll:altpll_component|pll3_altpll:auto_generated|pll1" input clock inclk[0] is not fully compensated because it is fed by a remote clock pin "Pin_T2".
Knowing that the input clock is connected on T1/T2 differential clock pin (DIFFCLK_1p and DIFFCLK_1n). Is it not allowed to connect two pll IPs to the same input clock ?
Thank you.
Hi ,
I done the below analysis from my side to debug the issue .
- Remove the pin constraints from the assignment editor , to isolate any pin mapping issue : But I found warning is present
- Analyzed the PLL logic in the design and found that same clock is been connected to to two pll by using altclkctrl
- The out put frequency from two pll, not allowing to merge together
- So the input pin for the both pll is same , that makes the quartus to assign two different pll one is near to the input pin other little bit far as there is no pll available neart to the input pin .
- This makes the reason for the warning .
- And also I am kindly requesting to check the timing of the design
27 Replies
ADuflPlease don't close this thread. So far you provided a very light support which can be sum up as "move the pll closer to clock pins". You didn't even answer the related query which was "To do such thing you advise me to edit the .*sdc file, am I right ?".
This thread is still an ongoing issue. Thank you.
Rahul_S_Intel1Frequent Contributor
Hi ,
Kindly let me know is there any assistance needed from my side.
- ADufl
Hi,
Yes. In case of such design :
inst_altclkctra : altclkctra port map( inclk => fpga_clk2, outclk => gbl_clk_100 ); inst_pll : pll port map( inclk0 => gbl_clk_100, c0 => clk_200, c1 => clk_10, c2 => clk_100, c3 => clk_50, c4 => clk_20, locked => locked ); inst_pll2 : pll2 port map( inclk0 => gbl_clk_100, c0 => clk_400, locked => locked );What is your suggestion in term of *.sdc to move the pll closer to clock pins ?
- Rahul_S_Intel1
Hi,
Kindly let me know if you need further support
- ADufl
Yes, I need further support as stated on my answer 30/30/2020 08:57 (France time).
- Rahul_S_Intel1
Hi ,
Can you please send a sample project which i can replicate the same here, it will be easy for me to debug the issue .
- ADufl
Yes. I will provide such design next week.
Thank you.
- Rahul_S_Intel1
Hi ,
Kindly find the log message as attached ,I could not able to find any warning on the above project compilation , let me know if I am missing some thing.
Quartus version 18.1
- ADufl
Line 578 :
Critical Warning (176598): PLL "pll:inst_pll|altpll:altpll_component|pll_altpll:auto_generated|pll1" input clock inclk[0] is not fully compensated because it is fed by a remote clock pin "Pin_T2"
- Rahul_S_Intel1
Hi ,
I done the below analysis from my side to debug the issue .
- Remove the pin constraints from the assignment editor , to isolate any pin mapping issue : But I found warning is present
- Analyzed the PLL logic in the design and found that same clock is been connected to to two pll by using altclkctrl
- The out put frequency from two pll, not allowing to merge together
- So the input pin for the both pll is same , that makes the quartus to assign two different pll one is near to the input pin other little bit far as there is no pll available neart to the input pin .
- This makes the reason for the warning .
- And also I am kindly requesting to check the timing of the design
- ADufl
Thank you for your support, your last message answers my question.
- Rahul_S_Intel1
Hi ,
With the above support ,May I close the thread
- ADufl
Yes you can.
Thank you.
