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ADufl's avatar
ADufl
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6 years ago
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Is it allowed to connect two pll inclk0 to the same input clock ?

Hi,

I have a design on a EP4CE40 FPGA where I instantiated a second pll and mapped the inclk0 input to the same input clock as the first one. I get a Critical Warning (176598): PLL "pll3:inst_pll2|altpll:altpll_component|pll3_altpll:auto_generated|pll1" input clock inclk[0] is not fully compensated because it is fed by a remote clock pin "Pin_T2".

Knowing that the input clock is connected on T1/T2 differential clock pin (DIFFCLK_1p and DIFFCLK_1n). Is it not allowed to connect two pll IPs to the same input clock ?

Thank you.

  • Rahul_S_Intel1's avatar
    Rahul_S_Intel1
    5 years ago

    Hi ,

    I done the below analysis from my side to debug the issue .

    1. Remove the pin constraints from the assignment editor , to isolate any pin mapping issue : But I found warning is present
    2. Analyzed the PLL logic in the design and found that same clock is been connected to to two pll by using altclkctrl
      1. The out put frequency from two pll, not allowing to merge together
      2. So the input pin for the both pll is same , that makes the quartus to assign two different pll one is near to the input pin other little bit far as there is no pll available neart to the input pin .
      3. This makes the reason for the warning .
    3. And also I am kindly requesting to check the timing of the design

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  • ADufl's avatar
    ADufl
    Icon for New Contributor rankNew Contributor
    5 years ago

    Please don't close this thread. So far you provided a very light support which can be sum up as "move the pll closer to clock pins". You didn't even answer the related query which was "To do such thing you advise me to edit the .*sdc file, am I right ?".

    This thread is still an ongoing issue. Thank you.

  • ADufl's avatar
    ADufl
    Icon for New Contributor rankNew Contributor
    5 years ago

    Hi,

    Yes. In case of such design :

    inst_altclkctra : altclkctra
		port map(
			inclk  => fpga_clk2,
			outclk => gbl_clk_100
		);
 
	inst_pll : pll
		port map(
			inclk0 => gbl_clk_100,
			c0     => clk_200,
			c1     => clk_10,
			c2     => clk_100,
			c3     => clk_50,
			c4     => clk_20,
			locked => locked
		);
 
	inst_pll2 : pll2
		port map(
			inclk0 => gbl_clk_100,
			c0     => clk_400,
			locked => locked
		);

    What is your suggestion in term of *.sdc to move the pll closer to clock pins ?

    • ADufl's avatar
      ADufl
      Icon for New Contributor rankNew Contributor
      5 years ago

      Yes, I need further support as stated on my answer 30/30/2020 08:57 (France time).

  • Rahul_S_Intel1's avatar
    Rahul_S_Intel1
    Icon for Frequent Contributor rankFrequent Contributor
    5 years ago

    Hi ,

    Can you please send a sample project which i can replicate the same here, it will be easy for me to debug the issue .

    • ADufl's avatar
      ADufl
      Icon for New Contributor rankNew Contributor
      5 years ago

      Yes. I will provide such design next week.

      Thank you.

  • Rahul_S_Intel1's avatar
    Rahul_S_Intel1
    Icon for Frequent Contributor rankFrequent Contributor
    5 years ago

    Hi ,

    Kindly find the log message as attached ,I could not able to find any warning on the above project compilation , let me know if I am missing some thing.

    Quartus version 18.1

    • ADufl's avatar
      ADufl
      Icon for New Contributor rankNew Contributor
      5 years ago

      Line 578 :

      Critical Warning (176598): PLL "pll:inst_pll|altpll:altpll_component|pll_altpll:auto_generated|pll1" input clock inclk[0] is not fully compensated because it is fed by a remote clock pin "Pin_T2"

  • Rahul_S_Intel1's avatar
    Rahul_S_Intel1
    Icon for Frequent Contributor rankFrequent Contributor
    5 years ago

    Hi ,

    I done the below analysis from my side to debug the issue .

    1. Remove the pin constraints from the assignment editor , to isolate any pin mapping issue : But I found warning is present
    2. Analyzed the PLL logic in the design and found that same clock is been connected to to two pll by using altclkctrl
      1. The out put frequency from two pll, not allowing to merge together
      2. So the input pin for the both pll is same , that makes the quartus to assign two different pll one is near to the input pin other little bit far as there is no pll available neart to the input pin .
      3. This makes the reason for the warning .
    3. And also I am kindly requesting to check the timing of the design

  • ADufl's avatar
    ADufl
    Icon for New Contributor rankNew Contributor
    5 years ago

    Thank you for your support, your last message answers my question.

    • ADufl's avatar
      ADufl
      Icon for New Contributor rankNew Contributor
      5 years ago

      Yes you can.

      Thank you.