Is it allowed to connect two pll inclk0 to the same input clock ?

hI

Is it possible to connect to the global clock and connect to the PLL

Hi,

Do you mean such design :

	inst_altclkctra : altclkctra
		port map(
			inclk  => fpga_clk2,
			outclk => gbl_clk_100
		);
 
	inst_pll : pll
		port map(
			inclk0 => gbl_clk_100,
			c0     => clk_200,
			c1     => clk_10,
			c2     => clk_100,
			c3     => clk_50,
			c4     => clk_20,
			locked => locked
		);
 
	inst_pll2 : pll2
		port map(
			inclk0 => gbl_clk_100,
			c0     => clk_400,
			locked => locked
		);

Doesn't change much except the critical warning is now on pll (instead of pll2) :

Critical Warning (176598): PLL "pll:inst_pll|altpll:altpll_component|pll_altpll:auto_generated|pll1" input clock inclk[0] is not fully compensated because it is fed by a remote clock pin "Pin_T2"

But it puzzles me that the message links directly inclk[0] to the pin considering there is now a buffer between them...

Hi ,

May I know is the critical warning is violating the timing , if it is not I may suggest to take the clock from the Gclk .

Hi,

If I may resume that support, does "take the clock from the Gclk" mean "map you input clock (which in my case is fpga_clk2, pins T1 and T2 ie differential clock pin DIFFCLK_1p and DIFFCLK_1n) to the inclk port of an altclkctr IP and use the outclk port as inputs for both yout PLL IPs" ?

I that's the case, I did so and that didn't solved the issue. Am I sure that this critical warning is legitimate ?

Thank you.

Hi ,

I had analyzed the warning message and I feel , this will not be a a major problem if you don't care about compensation.

The main reason for the warning message is shown below.

The specified PLL and its specified input clock are driven by a remote clock input pin. As a result, the input clock delay may not be fully compensated by the PLL.

ACTION: If you do not care about compensation of the input clock(s), use the no compensation mode instead. Otherwise, connect the input clock to a dedicated clock input pin.

Hope it clarifies

May I know full part no:

Hi ,

I just verified the clock pin and found it is dedicated clock pins attached screen shot for your reference , can you change the PLL location near to clock pins,

Apology kindly find the screen shot ,attaching again if you still find in finding screen shot kindly let me know

Hi ,

Kindly let me know, if you need further assistance.

Thanks as per our policy, May I close the thread , if you have new query . I am kindly requesting to open an new thread.