Forum Discussion
New ContributorIs it allowed to connect two pll inclk0 to the same input clock ?
Hi ,
I done the below analysis from my side to debug the issue .
- Remove the pin constraints from the assignment editor , to isolate any pin mapping issue : But I found warning is present
- Analyzed the PLL logic in the design and found that same clock is been connected to to two pll by using altclkctrl
- The out put frequency from two pll, not allowing to merge together
- So the input pin for the both pll is same , that makes the quartus to assign two different pll one is near to the input pin other little bit far as there is no pll available neart to the input pin .
- This makes the reason for the warning .
- And also I am kindly requesting to check the timing of the design
Frequent ContributorHi ,
I had analyzed the warning message and I feel , this will not be a a major problem if you don't care about compensation.
The main reason for the warning message is shown below.
The specified PLL and its specified input clock are driven by a remote clock input pin. As a result, the input clock delay may not be fully compensated by the PLL.
ACTION: If you do not care about compensation of the input clock(s), use the no compensation mode instead. Otherwise, connect the input clock to a dedicated clock input pin.
Hope it clarifies
New ContributorBut my clock is connected to T1 and T2 ie differential clock pin DIFFCLK_1p and DIFFCLK_1n (my target is a EP4CE40). This is a dedicated clock input pin, isn't it ?
