Forum Discussion
ADufl
New Contributor
New ContributorIs it allowed to connect two pll inclk0 to the same input clock ?
Hi, I have a design on a EP4CE40 FPGA where I instantiated a second pll and mapped the inclk0 input to the same input clock as the first one. I get a Critical Warning (176598): PLL "pll3:inst_pll2|a...
Hi ,
I done the below analysis from my side to debug the issue .
- Remove the pin constraints from the assignment editor , to isolate any pin mapping issue : But I found warning is present
- Analyzed the PLL logic in the design and found that same clock is been connected to to two pll by using altclkctrl
- The out put frequency from two pll, not allowing to merge together
- So the input pin for the both pll is same , that makes the quartus to assign two different pll one is near to the input pin other little bit far as there is no pll available neart to the input pin .
- This makes the reason for the warning .
- And also I am kindly requesting to check the timing of the design
ADuflNew Contributor
New ContributorHi,
If I may resume that support, does "take the clock from the Gclk" mean "map you input clock (which in my case is fpga_clk2, pins T1 and T2 ie differential clock pin DIFFCLK_1p and DIFFCLK_1n) to the inclk port of an altclkctr IP and use the outclk port as inputs for both yout PLL IPs" ?
I that's the case, I did so and that didn't solved the issue. Am I sure that this critical warning is legitimate ?
Thank you.
