anat
New Contributor
6 months agoIOPLL output clock issue Stratix10
Hi Team,
I configured iopll IP for three output clocks, (outclk0)100MHz, (outclk1)200MHz and (outclk2)600MHz. Ref clock is 100MHz.
I see duty cycle variation in the generated clock of 200MHz from iopll. I'm capturing the clocks using signal tap analyzer at a frequncy of 600MHz, genrated by same iopll.
Why the duty cycle is varying from 50%?
Clock waveform
IOPLL Settings