Forum Discussion

anat's avatar
anat
Icon for New Contributor rankNew Contributor
6 months ago

IOPLL output clock issue Stratix10

Hi Team, I configured iopll IP for three output clocks, (outclk0)100MHz, (outclk1)200MHz and (outclk2)600MHz. Ref clock is 100MHz. I see duty cycle variation in the generated clock of 200MHz fro...
Other Ips
RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
6 months ago

SignalTap uses a clock to capture the data, so it's dependent on that clock rate. For logic, you want it to be the same clock that drives the logic you're tapping, as you need to synchronously tap it. For probing a clock, I'm not sure exactly what you're hoping to see. Normally people have the clock drive a counter and then just sample that with another clock, to calculate X transitions happened in Y time.


Regards,

Richard Tan