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anat's avatar
anat
Icon for New Contributor rankNew Contributor
1 year ago

IOPLL output clock issue Stratix10

Hi Team, I configured iopll IP for three output clocks, (outclk0)100MHz, (outclk1)200MHz and (outclk2)600MHz. Ref clock is 100MHz. I see duty cycle variation in the generated clock of 200MHz fro...
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sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
1 year ago

You're not going to be able to see accurate sampling for a signal that fast. Rely on the timing analyzer to verify your clocks, not Signal Tap, or output to a pin and view on a scope. Signal Tap is for functional debug of data signals, not analyzing clocks.