New ContributorInterfacing Avalon Streaming FIFO IP with GTS Ethernet Hard IP (Agilex 5, quartus v25.3)
Hello, I posted this question before on the Quartus Prime Forum but saw this forum and thought maybe this would be a better place to post it. Sorry if this is considered spam and not allowed:
I want to integrate the Avalon Streaming Single Clock FIFO IP (AVST FIFO IP) with the GTS Ethernet Hard IP (GTS EHIP) , but the GTS EHIP outputs signals rxstatus_valid and rxstatus_data, that don't interface with the AVST FIFO IP. The AVST FIFO IP is in a custom module that sits in between the GTS EHIP and the rest of the 1x10G Ethernet System Example Design: Agilex 5 FPGA E-Series Modular Development Kit (Link: https://altera-fpga.github.io/rel-25.3/embedded-designs/agilex-5/e-series/modular/ethernet/agx5e-ethernet-10g/ug-agx5e-ethernet-10g/). How should I handle these signals? Can I ignore them? Is there a example reference design that does this? Thank you for the help!
IP Blocks (left:EHIP, right:avst sc fifo ip):
SC FIFO Parameters:
