New Contributor
New ContributorTo interface the rx status and the sc fifo, you should uncheck "use packets" and leave the SC FIFI ready signal unconnected (as the RX side doesn't support backpressure). This means you need to process the frames at datarate.
For how to handle this interface, I would take a look at the following section:
Depending on your application, the rx status may not be required. If you are doing specific processing for VLAN/SLAN, PAUSE/PFC, Control, or Broadcast/Multicast frames, then this would be required.
New ContributorHi Chris,
Thank you for the reply! A few follow-up questions:
1. Can the rxstatus signals be not connected at all ? I am trying to add on to this design (Design Link: https://altera-fpga.github.io/rel-25.3/embedded-designs/agilex-5/e-series/modular/ethernet/agx5e-ethernet-10g/ug-agx5e-ethernet-10g/). Will not connecting it cause any system issues?
2. If I uncheck use packets parameter, how does the system figure out start and end of every packet? I am trying to do packet processing.
Thank you again
New ContributorLooking at the design, it doesn't appear the rx_status signals are needed. The routing is just using the IP address.
As for start/end of a packet for rx_status, you can use the endofpacket signal from rx_data.
