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opexsys's avatar
opexsys
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1 month ago
Solved

Interfacing Avalon Streaming FIFO IP with GTS Ethernet Hard IP (Agilex 5, quartus v25.3)

Hello, I posted this question before on the Quartus Prime Forum but saw this forum and thought maybe this would be a better place to post it. Sorry if this is considered spam and not allowed: I ...
Ethernet
Transceiver
  • ChrisR_Altera's avatar
    ChrisR_Altera
    1 month ago

    Looking at the design, it doesn't appear the rx_status signals are needed.   The routing is just using the IP address.

    As for start/end of a packet for rx_status, you can use the endofpacket signal from rx_data.   

opexsys's avatar
opexsys
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1 month ago

Hi Chris,

Thank you for the reply! A few follow-up questions:

1. Can the rxstatus signals be not connected at all ? I am trying to add on to this design (Design Link: https://altera-fpga.github.io/rel-25.3/embedded-designs/agilex-5/e-series/modular/ethernet/agx5e-ethernet-10g/ug-agx5e-ethernet-10g/). Will not connecting it cause any system issues?

2. If I uncheck use packets parameter, how does the system figure out start and end of every packet? I am trying to do packet processing.

Thank you again

paveetirrasrie_Altera's avatar
paveetirrasrie_Altera
Icon for Frequent Contributor rankFrequent Contributor
1 month ago

Hello,

 

I’m glad that your question has been addressed, I now transition this thread to community support. 
If you have a new question, feel free to open a new thread to get the support from Altera experts.
Otherwise, the community users will continue to help you on this thread. 

 

Thank you Chris for supporting!!!


Thank you.