Forum Discussion
Hi Priyanshi,
Thanks for reaching out.
I would recommend you refer to the Scalable Switch Intel® FPGA IP for PCI Express* User Guide for the methods to read the configuration space registers. Here are some useful sections from the user guide:
1.Scalable Switch IP Debug Toolkit:
You can use the Debug Toolkit to read configuration space registers, such as the PCI Express Capability Structure. For instructions on enabling and launching the Debug Toolkit, see Section 4.8.3 Debug Toolkit, in the user guide.
2.Register Access Interface (RAI):
The RAI allows you to read registers of the Scalable Switch IP in Upstream Port Type and Tile, including configuration space registers. Refer to Section 5.6, "Register Access Interface," for details on how to use the RAI, and Section 7 for a list of accessible registers.
Note that you need to log in to the Intel RDC to access the user guide below. Please refer to the User Guide Access Information: https://www.intel.com/content/www/us/en/docs/programmable/683515/24-3/user-guide-access-information.html
Scalable Switch Intel® FPGA IP for PCI Express* User Guide: https://www.intel.com/content/www/us/en/secure/content-details/735327/scalable-switch-intel-fpga-ip-for-pci-express-user-guide.html?wapkw=scalable%20switch%20ip
Thanks.
Best Regards,
Ven