Implementing MSI-X in Agilex 7 Rtile MCDAM PCIe based design

Anonymous​ I am attaching screenshot above. When I select Enable CII interface, it adds p0_user_cii port to my dut module, and the signals shown in signal and interface tab shows interface which is matching with what is described on https://www.intel.com/content/www/us/en/docs/programmable/683501/25-1-1/configuration-intercept-interface.html . The list of signals does not match with information provided on https://www.intel.com/content/www/us/en/docs/programmable/817911/25-1-1/configuration-intercept-interface-cii.html 

At this point seeing this p0_user_cii port at dut, I am understating that i need to write a custom RTL block that interfaces with this port on dut and intercept transactions going to MSI-X capability offset in Config space but i dont know what is the address at which MSI-X capability is located in PCIe config space.   

As i mentioned in original post table 71 on https://www.intel.com/content/www/us/en/docs/programmable/683501/25-1-1/configuration-intercept-inte... provides cii interface signal list and its details - after reviewing them I have following questions. 

1. pX_cii_wr_o    Output    Indicates that cii_dout_p0/1 is valid. This signal is asserted only for a configuration write request.
   • there is no mention of "pX_cii_rd_o" signal,   can pX_cii_wr_o signal be used to determine read request? if this signal is at logic 0 , does it mean that this is CFG read request?
2. pX_cii_addr_o[9:0]    Output    The double-word register address in the received TLP header on the CII. 
   • is this the address associated with CFW write? how do i know Config space offset at which MSI-X capability is located? So I can compare pX_cii_addr_o along with pX_cii_hdr_first_be_o to check if the CFG access to targeting "MSI-X Enable" or"MSI-X function mask" or not.
3. how do I use CII interface so it ignores all offsets other than MSI-X capability structure related