implement ram with logic blocks

Hi all!

I am designing an Avalon-MM interface with a page system: a page register is used as address of a memory and a data register is used to read/write the memory.

The memory I instanciate is an altsyncram.

For functional purpose I need a true dual port memory (1 port for Avalon-MM, 1 port for core processing).

    channel_dst_mac_addr_ram : altsyncram
    generic map
    (
        lpm_type                    => "altsyncram",
        intended_device_family      => "Stratix IV",
        power_up_uninitialized      => "TRUE",
        operation_mode              => "BIDIR_DUAL_PORT",
        outdata_reg_a               => "CLOCK0",
        clock_enable_input_a        => "BYPASS",
        address_reg_b               => "CLOCK0",
        indata_reg_b                => "CLOCK0",
        wrcontrol_wraddress_reg_b   => "CLOCK0",
        outdata_reg_b               => "CLOCK0",
        clock_enable_input_b        => "BYPASS",
        numwords_a                  => NB_PAGES,
        numwords_b                  => NB_PAGES,
        widthad_a                   => pos_log2(NB_PAGES),
        widthad_b                   => pos_log2(NB_PAGES),
        width_a                     => 48,
        width_b                     => 48
    )
    port map
    (
        clock0                      => ast_clk,
        address_a                   => channel_dst_mac_addr_ram_address_a,
        wren_a                      => channel_dst_mac_addr_ram_wren_a,
        data_a                      => channel_dst_mac_addr_ram_data_a,
        q_a                         => channel_dst_mac_addr_ram_q_a,
        address_b                   => channel_dst_mac_addr_ram_address_b,
        wren_b                      => channel_dst_mac_addr_ram_wren_b,
        data_b                      => channel_dst_mac_addr_ram_data_b,
        q_b                         => channel_dst_mac_addr_ram_q_b
    );

My problem is that the number of pages I need (i.e. the memory depth) is usually quite low, like 2 or 3, but Quartus uses M9K to implement that memory.

Is there an option to force the altsyncram to be implemented in logic blocks rather than in onchip RAMs, that I can turn on when NB_PGE is low?

The system is for Stratix IV, I use Quartus 10.1.

Thx