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Altera_Forum
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14 years ago

implement ram with logic blocks

Hi all! I am designing an Avalon-MM interface with a page system: a page register is used as address of a memory and a data register is used to read/write the memory. The memory I instanci...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Cool!!

I have listed all the parameters of the altsyncram core in order to understand everything, and I could not figure out what that one meant.

So now 1) I figured out what it is 2) it might solve my issue!!

Thanks!

I'll test that right now, and tell if it works

Julien