I cannot set 2 ffts with different input width and output width.
In this project, I used 2 FFT IP cores, settings is shown as below:
Length:64,Direction:Bi-directional,Data Flow:Variable Streaming,Input Order: Natural,Output Order:Natural,Representation:Fixed Point, Data Input Width: 8 bits, Twiddle Width:8 bits,Data Output Width: 15 bits
Length:64,Direction:Bi-directional,Data Flow:Variable Streaming,Input Order: Natural,Output Order:Natural,Representation:Fixed Point, Data Input Width: 14 bits, Twiddle Width:14 bits,Data Output: Width 21 bits
It can do a compilation successfully when I use Quartus Prime Standard Edition 18.1.0.
But it will give me 2 errors below when I use Quartus Prime Pro Edition 24.1.0:
Error(23415): Can't find Memory Initialization File or Hexadecimal (Intel-Format) File C:/intelFPGA_pro/project/sim_fft1/fft14in_altera_fft_ii_191_4jy74ay_opt_twr1.hex for ROM instance fft_reciever_inst|ifft2_inst|fft_ii_0|auk_dspip_r22sdf_top_inst|r22sdf_core_inst|gen_natural_order_core.gen_stages[1].gen_twiddles.stg_twidrom2|gen_optimized_memory_delayed.single_port_rom_component_real|new_ram_gen.new_ram_component|auto_generated|altsyncram1|ram_block2a0
Error(23415): Can't find Memory Initialization File or Hexadecimal (Intel-Format) File C:/intelFPGA_pro/project/sim_fft1/fft14in_altera_fft_ii_191_4jy74ay_opt_twr2.hex for ROM instance fft_reciever_inst|ifft2_inst|fft_ii_0|auk_dspip_r22sdf_top_inst|r22sdf_core_inst|gen_natural_order_core.gen_stages[2].gen_twiddles.stg_twidrom2|gen_optimized_memory_delayed.single_port_rom_component_real|new_ram_gen.new_ram_component|auto_generated|altsyncram1|ram_block2a0