I am using IOPLL Intel FPGA IP for Aria 10 SoC device. I need a clock of 307.2MHz/30.72MHz with a ref Clock of 10/100MHz . How can I get the exact clock?

Question

With many possible combinations as well, I could get Actual output clock as 307.5M/307.142M/307.189M but not exact value. M,N,C Counter values can be edited only as integer values but not fractional values. Please suggest what can be done.

engwei_o_intel · Answer

Hi AnamikaSorry for late response. Can you try to set the PLL mode to Fractional-N PLL?ThanksEng Wei

abhus · Answer

Thanks for the response.Actually, in IOPLL there is no option to set PLL mode as Fractional mode.But there is one fPLL under Transceiver section in which we can use Fractional mode.Is it ok to use fPLL for driving user logic?When I tried using fPLL it is giving Fitter placement issues as shown below?"Error(11215): Input port "REFCLK" of "CMU_FPLL_REFCLK_SELECT" cannot connect to PLD port "O" of "IO_INPUT_BUFFER" for atom "fpga_clk~input". "

engwei_o_intel · Answer

Hi AnamikaMay I know which version of Quartus tools that you are currently using? For PLL selection, for example in Quartus 18.1 version, we can use:Basic Functions -&gt; PLL -&gt; PLL Intel FPGA IPAfter selecting the IP above, you can refer to doc below for more calculation setting:https://www.intel.com/content/dam/altera-www/global/en_US/kdb/rd08062012_921/how_fractional_divisor_is_calculated_in_quartus_rev4.pdfThanks.Eng Wei

abhus · Answer

Hi Eng WeiI am using Quartus Prime 19.1.0 and Arria 10 SoC Device.For PLL IP Selection, Basic Functions -&gt; PLL -&gt; IOPLL Intel FPGA IP as shown in the image attached.For Parameter settings for IOPLL, please refer attached image.As per this, I am not getting fractional calculation settings.Could you please check these snapshots and revert.Thanks and RegardsAnamika Bhushan

engwei_o_intel · Answer

Hi Anamika BhushanFor Arria 10 device, yup, you can use the fpll under Transceiver PLL. Regarding the fitter issue when you were using the fpll, can you share with us the parameter setting that you are using for the fpll? Or possibly a sample design that you are connecting the fpll?Thanks.Eng Wei

Forum Discussion

I am using IOPLL Intel FPGA IP for Aria 10 SoC device. I need a clock of 307.2MHz/30.72MHz with a ref Clock of 10/100MHz . How can I get the exact clock?

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