I am using IOPLL Intel FPGA IP for Aria 10 SoC device. I need a clock of 307.2MHz/30.72MHz with a ref Clock of 10/100MHz . How can I get the exact clock?

New Contributor

5 years ago

Hi Eng Wei

I have created one simple counter logic, to make sure fPLL works for user logic. I have attached parameter selction pic for fPLL.

Clock path is FPGA pin -> fPLL input

Output clock from fPLL is used for running a 4 bit counter. Counter bits are given to on board LEDs.

Error: Error(11215): Input port "REFCLK" of "CMU_FPLL_REFCLK_SELECT" cannot connect to PLD port "O" of "IO_INPUT_BUFFER" for atom "fpga_clk~input".

Extra Info(13133): Output port's "O[0]" atom name is "fpga_clk~input".

Extra Info(13134): Input port's "REFCLK[0]" atom name is "u0|xcvr_fpll_a10_0|xcvr_fpll_a10_0|fpll_refclk_select_inst".

Extra Info(12877): Output port "O[0]" of "IO_INPUT_BUFFER" can connect to:

Extra Info(12878): Port "INCLK[0]" of "CLKBUFBLOCK"

Extra Info(12878): Port "INCLK[0]" of "CLKSELBLOCK"

Extra Info(12878): Port "INCLK[1]" of "CLKSELBLOCK"

Extra Info(12878): Port "INCLK[2]" of "CLKSELBLOCK"

Extra Info(12878): Port "INCLK[3]" of "CLKSELBLOCK"

Extra Info(12878): Port "DATAIN[0]" of "DELAY_CHAIN"

Extra Info(12878): Port "I_INCLK[0]" of "CLKBURSTBLOCK"

Extra Info(12878): Port "I_RXN[0]" of "HSSI_PMA_RX_BUF"

Extra Info(12878): Port "I_RXP[0]" of "HSSI_PMA_RX_BUF"

Extra Info(12878): Port "I_RX_N_BIDIR_IN[0]" of "HSSI_PMA_TX_BUF"

Extra Info(12878): Port "I_RX_P_BIDIR_IN[0]" of "HSSI_PMA_TX_BUF"

Extra Info(12878): Port "I_REFCLK_INN[0]" of "HSSI_REFCLK_DIVIDER"

Extra Info(12878): Port "I_REFCLK_INP[0]" of "HSSI_REFCLK_DIVIDER"

Extra Info(12878): Port "I_RXP[0]" of "HSSI_PMA_CDR_PLL"

Extra Info(12878): Port "I_PIN_PERST_N[0]" of "HSSI_GEN3_X8_PCIE_HIP"

Extra Info(12879): Input port "REFCLK[0]" of "CMU_FPLL_REFCLK_SELECT" can connect to:

Extra Info(12880): Port "O_REFCLK_A[0]" of "HSSI_REFCLK_DIVIDER"

Thanks and Regards

Anamika Bhushan

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