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FPGA1's avatar
FPGA1
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5 years ago

hps ddr3

hi

In HPS, I connect an Avalon-mm-bridge host to f2h-Axi-slave, and export the slave of Avalon-mm bridge from the machine. Can I read and write DDR3 on the HPS side directly？

5 Replies

  • BrusC_Intel's avatar
    BrusC_Intel
    Icon for New Contributor rankNew Contributor
    5 years ago

    Hello, FPGA1.


    Thank you for posting in the Intel Community Support forum.


    I will route your thread to a section for similar issues/questions so it can get answered as soon as possible.


    Best regards,


    Bruce C.

    Intel Customer Support Technician


  • EBERLAZARE_I_Intel's avatar
    EBERLAZARE_I_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi,

    It is recommended that you do all interconnect and bring it inside Platform Designer than exporting it out. If you are trying to access the DDR3 of the HPS , you will need a EMIF IP for the HPS and set the settings a per spec of your DDR connect it to the HPS.

    • FPGA1's avatar
      FPGA1
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      5 years ago

      Hi，

      Sorry, I just logged in today

      I'm a little bit delayed now. I didn't continue with it

      But I want to ask, can't Avalon mm bridge be imported from SoC system as data input on FPGA side? I just searched the EMIF IP, but I didn't find it. Can I explain this in detail

    • FPGA1's avatar
      FPGA1
      Icon for New Contributor rankNew Contributor
      5 years ago
      Spoiler


      I just went to cut a picture for you，We are eager to solve this problem ，thanks