How to use 4x10g phy as bare 40g phy without MAC ip

Hi EEnam,

I looked at your sim waveform. 0100009C value appeared on XGmii interface but Intel FPGA NativePHY IP doesn't has XGmii interface. It only contains the transceiver channel tx_parallel_data or rx_parallel_date to/from FPGA core logic.

1. I believe transceiver data output to XGmii interface conversion is done by your own IP design logic, right ? Have you isolate the problem is on transceiver data output or on XGmii interface conversion logic itself ? You may want to cross check your design again
2. Then other thing that I checked with you earlier was did you implement reconciliation sublayer (RS) to handle local and remote fault as "0100009C" represent local fault signaling ?
3. Finally regarding transceiver channel setting difference btw 10G NativePHY ip preset vs LL 40G Ethernet MAC + PHY IP

• There is no hard rule on how to implement the PHY design logic. It's really up to IP developer on how they want to implement the design
  • 10G NativePHY ip preset use 64 bits width data output to FPGA core logic while enable certain hard PCS function in transceiver channel
  • LL 40G Ethernet MAC + PHY IP on the other hand use 40 bits width data output to FPGA core logic while most of the PCS function is created in FPGA core logic instead of using hard PCS function in transceiver channel. Unfortunately how the IP developer build the whole 40G PHY design is proprietary info by Intel. (attached is high level block diagram of 40G Eth IP)

My debug suggestion is you may want to cross check your XGmii interface conversion logic design again.

Also does it make a difference if you generate other input value (not 0100009C) to xgmii_tx_data ?

Typically Intel doesn't just simulate Ethernet PHY only. Our example design always come with both Ethernet MAC and PHY together.

Thanks.

Regards,

dlim

Hi dlim.

Yes, you are right, “qsfp” signals in screen above is direct output from transceiver and rx-tx is looped in logic. I modify arrays names and control signals assignments for better clarity.

Only thing that is strange to me is that control signals is indicating data transfer (https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/arria-10/ug_arria10_xcvr_phy.pdf page 83, Table 60) when I think this is control word (http://www.ieee802.org/3/ak/public/jan03/WPcls48_1_0.pdf Table 48–2).

Apart from that, the control and data signals are just looped so it should work anyway.

Yes my case is different. It's strange but Quartus Pro 19.1 requires different settings for PMA than Quartus standard 18.1. I'm not sure this because of standard -> pro migration or maybe version 18.1 to 19.1 increment. However those are settings I used on my DE5A-net board to make qsfp work. I probably should have run some transceiver toolkit to adjust them, but I tried some random changes (based on DE5A-net evaluation bard examples) and it works so far:

    # Rx
    set_instance_assignment -name XCVR_A10_RX_LINK LR -to QSFPA_RX_p[0]
    set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFPA_RX_p[0]
    set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFPA_RX_p[0]
    # Tx
    set_instance_assignment -name XCVR_A10_TX_LINK LR -to QSFPA_TX_p[0]
    set_instance_assignment -name XCVR_A10_TX_TERM_SEL R_R1 -to QSFPA_TX_p[0]
    set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFPA_TX_p[0]
    # Clock
    set_instance_assignment -name XCVR_A10_REFCLK_TERM_TRISTATE TRISTATE_OFF -to QSFPA_REFCLK_p
 
#tx: vod control, 28
set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 28 -to QSFPA_TX_p[0]
#tx: pre-emphasis first post-tap, -7
set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_NEG -to QSFPA_TX_p[0]
set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 7 -to QSFPA_TX_p[0]
#tx: pre-emphasis pre-tap, -2
set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_PRE_TAP_1T FIR_PRE_1T_NEG -to QSFPA_TX_p[0]
set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1T 2 -to QSFPA_TX_p[0]
#rx: DC gain(0~4), 4
set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFPA_RX_p[0]
#EqControl(0~28) = 15
set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_28 -to QSFPA_RX_p[0]
#rx: VGA(0~7) = 7
set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_7 -to QSFPA_RX_p[0]
# ?
set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_EQZ_1S_SEL RADP_CTLE_EQZ_1S_SEL_7 -to QSFPA_RX_p[0]
# ?
set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_63 -to QSFPA_RX_p[0]
# ?
set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFPA_RX_p[0]