Forum Discussion
EEnam
New Contributor
6 years agoLet's focus on simulation which i think is failing too. My PHY 10g simulation test was to loopback TX to RX serial data, while set "0707070707070707" 'idle' state on parallel TX input, after tx_ready and rx_ready signals goes '1'. Lockedtoref and lockedtodat goes '1', parallel RX output changes from “0100009C0100009C” to "0707070707070707" 'idle' state (test pass).
When I trying to do same test on PHY 4x10g IP configured as described in first post, the parallel RX output stays constant “0100009C0100009C” while tx_ready, rx_ready, lockedtoref and lockedtodat goes '1' (every channel similarly). Mo matter what i put on parallel TX input, output doesn’t change.