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EEnam's avatar
EEnam
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6 years ago

How to use 4x10g phy as bare 40g phy without MAC ip

Hi, I successfully start a 10g PHY ip in way that i can receive the packet. Now I’ve been trying to configure 40g PHY without mac just to get any changes of data at IP output and I can’t achieve that...
EEnam's avatar
EEnam
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6 years ago

(40G simulation screen - controls signals with 'X' are unused and unconceded in phy, I loop 8bit controls (all that ip give) by array (0) position)

Hi, according to what you describe in second point in post above – I am only putting “0100009C” or “0200009C” before “block lock” and” rx data” change to IDLE state (x“07”), same as in my 10g testbench(10G works,40g not work). I attached two screen shots from this testbench.

When I studying LL40G PHY&MAC example I found file with PHY configuration for 4x10G xcvr_native_a10 and its not configured as described in first post (from “ug_arria10_xcvr_phy.pdf”). I attached this two files in zip to easy compare in any comparing tool.

Should I use this configuration from LL40g?

Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi EEnam,

I looked at your sim waveform. 0100009C value appeared on XGmii interface but Intel FPGA NativePHY IP doesn't has XGmii interface. It only contains the transceiver channel tx_parallel_data or rx_parallel_date to/from FPGA core logic.

  1. I believe transceiver data output to XGmii interface conversion is done by your own IP design logic, right ? Have you isolate the problem is on transceiver data output or on XGmii interface conversion logic itself ? You may want to cross check your design again
  2. Then other thing that I checked with you earlier was did you implement reconciliation sublayer (RS) to handle local and remote fault as "0100009C" represent local fault signaling ?
  3. Finally regarding transceiver channel setting difference btw 10G NativePHY ip preset vs LL 40G Ethernet MAC + PHY IP
  • There is no hard rule on how to implement the PHY design logic. It's really up to IP developer on how they want to implement the design
    • 10G NativePHY ip preset use 64 bits width data output to FPGA core logic while enable certain hard PCS function in transceiver channel
    • LL 40G Ethernet MAC + PHY IP on the other hand use 40 bits width data output to FPGA core logic while most of the PCS function is created in FPGA core logic instead of using hard PCS function in transceiver channel. Unfortunately how the IP developer build the whole 40G PHY design is proprietary info by Intel. (attached is high level block diagram of 40G Eth IP)

My debug suggestion is you may want to cross check your XGmii interface conversion logic design again.

Also does it make a difference if you generate other input value (not 0100009C) to xgmii_tx_data ?

Typically Intel doesn't just simulate Ethernet PHY only. Our example design always come with both Ethernet MAC and PHY together.

Thanks.

Regards,

dlim