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EEnam's avatar
EEnam
Icon for New Contributor rankNew Contributor
6 years ago

How to use 4x10g phy as bare 40g phy without MAC ip

Hi, I successfully start a 10g PHY ip in way that i can receive the packet. Now I’ve been trying to configure 40g PHY without mac just to get any changes of data at IP output and I can’t achieve that...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi SSilu,

I suspect your case is different from EEnam. He is running sim not hardware testing, so there is no concern from signal integrity perspective.

For your case, hardware testing with high BER is bad. You want to confirm nothing wrong with your board setup/design that may impact signal integrity.

If you confirm board side is good then you can switch to debug Quartus design.

  • You can cross check the transceiver PMA analog setting between v18.1 and v19.1 design to check for potential setting mismatch
  • Else you can also start to build the design from scratch in v19.1 to ensure there is no design files corruption during Quartus design upgrade from v18.1 to v19.1

Thanks.

Regards,

dlim

  • SSilu's avatar
    SSilu
    Icon for New Contributor rankNew Contributor
    6 years ago

    Yes my case is different. It's strange but Quartus Pro 19.1 requires different settings for PMA than Quartus standard 18.1. I'm not sure this because of standard -> pro migration or maybe version 18.1 to 19.1 increment. However those are settings I used on my DE5A-net board to make qsfp work. I probably should have run some transceiver toolkit to adjust them, but I tried some random changes (based on DE5A-net evaluation bard examples) and it works so far:

        # Rx
    set_instance_assignment -name XCVR_A10_RX_LINK LR -to QSFPA_RX_p[0]
    set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFPA_RX_p[0]
    set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFPA_RX_p[0]
    # Tx
    set_instance_assignment -name XCVR_A10_TX_LINK LR -to QSFPA_TX_p[0]
    set_instance_assignment -name XCVR_A10_TX_TERM_SEL R_R1 -to QSFPA_TX_p[0]
    set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFPA_TX_p[0]
    # Clock
    set_instance_assignment -name XCVR_A10_REFCLK_TERM_TRISTATE TRISTATE_OFF -to QSFPA_REFCLK_p
 
#tx: vod control, 28
set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 28 -to QSFPA_TX_p[0]
#tx: pre-emphasis first post-tap, -7
set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_NEG -to QSFPA_TX_p[0]
set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 7 -to QSFPA_TX_p[0]
#tx: pre-emphasis pre-tap, -2
set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_PRE_TAP_1T FIR_PRE_1T_NEG -to QSFPA_TX_p[0]
set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1T 2 -to QSFPA_TX_p[0]
#rx: DC gain(0~4), 4
set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFPA_RX_p[0]
#EqControl(0~28) = 15
set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_28 -to QSFPA_RX_p[0]
#rx: VGA(0~7) = 7
set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_7 -to QSFPA_RX_p[0]
# ?
set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_EQZ_1S_SEL RADP_CTLE_EQZ_1S_SEL_7 -to QSFPA_RX_p[0]
# ?
set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_63 -to QSFPA_RX_p[0]
# ?
set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFPA_RX_p[0]