Forum Discussion
JET60200
Contributor
4 years ago" One possible solution is to generate the Secondary Bus Reset from the host. It is available at the Bridge Control register Bit 6. "
-> Hello @SengKok_L_Intel ,
Sorry for the delay , but which document describes the mentioned " Bridge Control Register " ?
Pls help to point it out, so i could check it detailedly. thanks
SengKok_L_Intel
Regular Contributor
4 years agoYou can search the "secondary bus reset" or "bridge control register" from the PCIe spec.
- JET602004 years ago
Contributor
Thanks @SengKok_L_Intel for quick feedback,
I have no more questions on this ticket, thanks for kindly support!