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The intention of the auto generated rootport testbench is the simulation the PCIe Hard IP by connecting to the APPS components, the testbench only covers the .qsys example design under <install_dir>/ip/altera/altera_pcie/altera_pcie_<dev>_ed/example_design/, it doesn't covers the simulation of whole design environment such as when users add in their own application components.
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Currently, even I'm in the phase of setting up simulation environment for my PCIe design for Arria 10 GX.
Could you please tell me what tests the basic test bench for PCIe does and where can I find those test logic? This would help me tweak it to add my own pcie test cases.
Honored Contributor
