Forum Discussion

rMa1's avatar
rMa1
Icon for New Contributor rankNew Contributor
5 years ago
Solved

How to set descriptor length dynamically in PCIe Hard IP (AVMM-DMA interface)

In my system, data stream has different length in the three mode, for example, we need descriptor length=128 in mode1, and descriptor length=32 in mode2, descriptor length=100 in mode3, mode set by H...
  • KhaiChein_Y_Intel's avatar
    KhaiChein_Y_Intel
    5 years ago

    Hi,


    We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you


    Best regards,

    KhaiY


KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi Vicky,


Upon checking, you may use RD_DMA_LAST_PTR (Read) or WR_DMA_LAST_PTR (Write) to control the descriptor length. If 128 descriptors are specified and all of them execute, then descriptor ID 127 is written to the RD_DMA_LAST_PTR or WR_DMA_LAST_PTR register to start the DMA.


For example, if RD_DMA_LAST_PTR reads 4, the last descriptor requested is 4. To specify 5 more descriptors, software should write a 9 into the RD_DMA_LAST_PTR register. The DMA executes 5 more descriptors. To have the read DMA record the done bit of every descriptor, program this register to transfer one descriptor at a time. RD_TABLE_SIZE specifies the size of the Read descriptor table. The descriptor ID loops back to 0 after reaching RD_TABLE_SIZE. For example, if the RD_DMA_LAST_PTR value read is 126 and you want to execute three more descriptors, software must write 127, and then 1 into the RD_DMA_LAST_PTR register


You may refer to Intel® Arria® 10 or Intel® Cyclone® 10 GX Avalon® Memory Mapped (AvalonMM) DMA Interface for PCI Express* Solutions User Guide for details.

https://www.intel.cn/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_a10_pcie_avmm_dma.pdf


Thanks

Best regards,

KhaiY


  • rMa1's avatar
    rMa1
    Icon for New Contributor rankNew Contributor
    5 years ago

    Hi KhaiChein,

    Do you mean RD_TABLE_SIZE could be programed at any time? For example, if I want to use descriptor length is 128, set RD_TABLE_SIZE=128 and RD_DMA_LAST_PTR=127(same as WR_DMA_PTR); then I want to use descriptor length is 15 after descriptor ID loop back to 0, I will set RD_TABLE_SIZE=15 and RD_DMA_LAST_PTR=14, is it right?

    I want to know if descriptor table length could specific dynamically, in the manual, RD_TABLE_SIZE could be set (only) one time, should be set the maximum size, all descriptor ID need to go through until RD_TABLE_SIZE, although some times actually use descriptor length are less than RD_TABLE_SIZE(set by before), I mean it is no need to go though all descriptor ID if we could set RD_TABLE_SIZE any time.

    Please correct me.

    Vicky