Contributorhttps://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_pfl.pdf
https://www.intel.com/content/www/us/en/programmable/documentation/sss1411439280066.html
Differences in below constraints between the 2 docs. Which constraints are right ?
flash_nce
flash_addr
flash_data
fpga_data
fpga_dclk
ContributorNoticed today (12 days later) after I opened the 2 docs again that you changed one of them to match the other BUT I never received a reply from you to let me know that you did this.
ContributorBoth documents state now :
eg https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_pfl.pdf on page 28 :
Bidirectional synchronous: flash_data Read mode (PFL to Flash ROM) is listed here on page 28.
set_max_delay -from <port> -to pfl_clk
Is this right ?
PFL to Flash ROM direction looks to be output from the PFL (ie flash_data is out for READ mode. Isn’t this the case?) so the set_max_delay constraint suggested above should be :
set_max_delay -from pfl_clk -to <port>
Isn’t this the case here ?
ContributorOr I think :
Bidirectional synchronous: flash_data Read mode (Flash ROM to PFL) should be listed here on page 28 and NOT PFL to Flash ROM
set_max_delay -from <port> -to pfl_clk IS THEN CORRECT
Write Mode should then state (PFL to Flash ROM) and NOT Flash ROM to PFL
Is this correct?
ContributorWrt :
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_pfl.pdf
fpga_dclk constraint for input clock to DCLK ratio = 1 (see page 29)
create_generated_clock - source pfl_clk -invert <fpga_dclk_port>
I have used same constraint as above BUT have the following question :
Q/ Is there a special reason to why -invert is suggested here ?
Like a reply to this please.
Super ContributorKevin
Im checking this and let you know.
