How to properly constrain the PFL ? Differences between 2 docs. Which one is right?

Wrt :

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_pfl.pdf

fpga_dclk constraint for input clock to DCLK ratio = 1 (see page 29)

create_generated_clock - source pfl_clk -invert <fpga_dclk_port>

I have used same constraint as above BUT have the following question :

Q/ Is there a special reason to why -invert is suggested here ?

Like a reply to this please.